module sx_register(clk, din, dout,s0,s1,rst);  
 
	input clk,rst,s0,s1;
	input [3:0] din;
	output reg[3:0] dout;
 
 always @(posedge clk)  
  begin
		if(rst)
			dout = 0;
		else begin
			case({s0,s1})
				2'b00: dout = dout;
				2'b01: dout = {din[0], din[3:1]};    //right
				2'b10: dout = {din[2:0],din[3]};    //left
				2'b11: dout = din;
				default: dout = dout;
			endcase
		end
  end  
 
endmodule
